ASIC RTL/SoC Design Engineer

ASIC RTL/SoC Design Engineer

Fremont, CA

Full Time

Responsibilities:

Lead RTL design, simulation, and verification efforts for ASIC/SoC products, ensuring robust and efficient designs

Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility

Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs

Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout

Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications

Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product

Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth

Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability

Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency

Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery

Requirements

:MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital desig

nExperience with Verilog and system Verilo

gExperience with VCS, Verdi or other industry standard tool

sExperience with pre-layout simulation and post-layout simulatio

nUnderstanding of the design flow. Ability to work with the backend tea

mFamiliarity with AMBA APB AXI Protoco

lFamiliarity with RISC/Arm or other core architecture

sAbility to create innovative architecture and solutions to customer requirement

sAbility to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team

.Experience in one or more of the following areas considered a strong plus

:FPGA/ASIC design of image processing system

sWorking knowledge of SoC architecture such as CPU, GPU or accelerator

sFamiliarity with: UVM, place-and-route, STA, EM/IR/Powe

r