Design Verification Engineer

YOU MUST HAVE WORKING KNOWLEDGE OF EDA tools and Semiconductors!

PLEASE HAVE EDA/SEMICONDUTOR EXPERIENCE WHEN APPLYING!

Design Verification Engineer…. UVM… Bay Area #7810

My client is a very promising, innovative, well-funded startup backed by top-tier investors and trusted by big chip design companies and leading AI chip startups, working at the cutting-edge intersection of AI and semiconductor design. They are looking for an experienced Design Verification Engineer with deep expertise in UVM.

They are building a new class of verification platforms using LLMs to automate and accelerate chip development. The team is composed of experts in the fields of AI, software development, and semiconductor design and their platform is already deployed across multiple Fortune 100 and cutting-edge design teams. You’ll join a small, elite team of engineers solving some of the most complex challenges in chip verification by integrating traditional flows with generative AI.

Their mission is to accelerate the development of complex silicon by orders of magnitude: cutting cost, time and engineering effort, for the world’s leading chip teams- - Their customers are several, which they have already deployed: Qualcomm, Nvidia, Google, Meta, and the Allen Institute for AI; 10+ innovative customers—from Fortune 100s to cutting-edge AI silicon startups --Their backers are top investors including Khosla Ventures, Cerberus, and Clear Ventures. - Their founders have an amazing background and pedigree, perfect for this venture.

Job Description:

They are looking for skilled and passionate Verification Engineers or Chip Designers who have significant experience with VLSI front-end design flows, specifically UVM, to collaborate closely with their ML and software teams. In this unique role, you will apply LLM’s for DV; you will work on advanced technologies that leverage your design verification experience with ML for innovative chip design solutions; You will have the opportunity to learn from experienced ML leads and directly contribute to projects for their existing customers.

This position is ideal for a chip designer who is eager to push beyond traditional roles and explore the frontier of AI-integrated semiconductor design. This terrific opportunity will give you the opportunity to make a real and significant contribution, as they unleash this existing, yet totally new approach to CHIP DESIGN.

Your Role:

As a UVM Specialist, you will own the development, refinement, and deployment of UVM testbenches within an AI-enhanced verification environment. You'll collaborate closely with machine learning and software engineers to guide LLMs in automating the DV process, support customer deployments, and shape the future of chip verification.

Key Responsibilities:

Build and optimize UVM-based testbenches that integrate with AI-driven workflows.

Collaborate with ML and software teams to enhance LLM-generated verification artifacts such as test plans, monitors, and coverage models.

Guide verification best practices while supporting AI-driven code generation and debug automation.

Work directly with customers to understand DV needs and deploy innovative solutions in real designs.

Contribute to internal test suites, benchmarks, and feedback loops for AI model improvements.

Stay up to date on both DV methodology and advances in AI as applied to hardware design.

Engage directly with customer projects, applying your expertise to develop practical and innovative solutions.

Qualifications:

Proven ability to architect UVM environments from scratch, debug simulations, and close coverage.

Deep knowledge of verification strategies, assertions, constrained-random test generation, and coverage-driven development.

Practical experience with EDA tools (Synopsys, Cadence, Siemens).

Proficiency in scripting and automation (Python, etc.).

Familiarity with formal verification and interest in LLMs or AI-based workflows is a strong plus.

Excellent communication and collaboration skills, including customer-facing work.

Bachelor’s or Master’s degree in EE, CE, or a related field.

To learn more about this and other openings, contact Mark Gilbert anytime by email, or call 305-598-2222x3. Please include your resume so we can have a more precise conversation.