Signal Integrity Engineer

Compensation & Job Details:

Direct hire - $140K-$212K, 20% sign on bonus, LTI Grant

Hiring Locations: Harrisburg, PA; Austin, TX

Exact rate is based on several factors, including skills, experience, and education. The team hires in Levels 1-4 so rate is also contingent on hiring level.

Benefit packages for this role will start on the 1st day of employment and include medical, dental, and vision insurance, as well as HSA, FSA, and DCFSA account options, and 401k retirement account access with employer matching. Employees in this role are also entitled to paid sick leave and/or other paid time off as provided by applicable law.

Job Description: As a Staff Product Development Engineer in the Signal Integrity Center of Excellence (SI COE), you will lead advanced signal integrity (SI) research, modeling, and validation for next-generation high-speed interconnects used in AI data centers, and high-performance computing (HPC). Your role involves independently conducting SI studies and design platforming, including geometry analysis and simulation-driven optimizations. You will be responsible for exploring new SI methodologies, conducting literature reviews, formulating research plans, programming, simulating, and testing to develop innovative solutions—even in ambiguous environments. You will collaborate closely with mechanical, manufacturing, materials, and operations teams to drive the adoption of cutting-edge SI technologies. As a subject matter expert, you will oversee the entire SI lifecycle, from initial analysis and modeling to design, simulation, prototype fabrication, and final validation. You will tackle complex design challenges, leveraging advanced simulation tools to optimize designs for manufacturability and performance

Responsibilities:

Drive SI design, simulation, and validation for next-gen high-speed interconnects (112G/224G PAM4, PCIe Gen6/7, Co-Packaged, and Near Package) through the product development cycle.

Conducting SI COE analysis, including

Performing signal integrity simulations and analysis for high-speed interconnect product development. This includes determining the correct simulation methodology and setup to use, as well as a good understanding of the criteria for each interface.

Modeling the connector with the consideration of manufacture impact and application impact.

Providing solutions to the SI challenges. This includes identifying the problems, making research plans, developing new technologies, and training and sharing the findings with the SI community.

Develop novel interconnect solutions by optimizing mating interfaces, lead frames, and PCB transitions for resonance-free, low-loss performance.

Enhance bulk cable design & termination techniques to minimize skew, impedance mismatches, and signal degradation.

Advance high-frequency testing methodologies beyond 67 GHz with innovative non-PCB-based test fixtures.

Utilize AI & big data analytics for predictive SI modeling, auto-routing, and performance optimization.

Optimize material selection & electromagnetic design to improve noise isolation, signal integrity, and high-frequency response.

Collaborate with NPD teams & industry partners to influence SI strategies, technology roadmaps, and next-gen product designs.