Onsite Mid-level Verification Engineer, UVM, SystemVerilog

Location: Newark, CA 94560

Type: Contract

JO#: 25-08288:CD

Title: Onsite Mid-level Verification Engineer, UVM, SystemVerilog

Description:

Onsite Mid-level Verification Engineer with 5-8 years of experience of pure verification in FPGA.

This is a pure Verification Engineer only role.

This position is onsite in the greater San Jose Bay Area.

What you will be doing:

Purely verification of FPGA

Programming using SystemVerilog

Develop OO testbench infrastructure

Develop test cases using UVM

Scripting

What you will need:

5-8 years in pure Verification

Solid in SystemVerilog programming

Experience with UVM,

Universal Verification Methodology

Experience developing OO testbench infrastructure

Experience with Interfaces such as I2C - Inter-Integrated Circuit, MDIO - Management Data Input/Output, SPI - Serial Peripheral Interface, PCIe - Peripheral Component Interconnect Express

Scripting using Python or Perl