Display Silicon Engineer

The Display Silicon team, within the broader Display and Optics organization, is seeking a Display Silicon Engineer to support the development of Meta’s proprietary display silicon backplanes for wearable AR displays.

As a member of the Display Silicon team, you will collaborate closely with display silicon architects, electrical engineers, optical scientists, device engineers, pixel pipeline engineers, the visual quality team, and external silicon design vendors to develop and deliver silicon display solutions.

This role provides a unique opportunity to contribute to both forward-looking research and product-critical projects, requiring collaboration across multiple teams within Meta Reality Labs.

Responsibilities:

Display Silicon Engineer Responsibilities:

Drive block-level specification of display silicon designs

Work closely with silicon vendors to fully-specify and implement design

Support cross functional teams integrating our silicon into larger systems

Operate in a highly collaborative, cross-functional role

Work with chip and block architects to understand macro floorplan, power distribution, and signal interfaces

Develop microarchitectural models of display systems for validation and verification

Leverage models and automation to drive data-informed specification of display backplanes

Up to 15% travel (domestic and international)

Qualification and experience:

Minimum Qualifications:

5+ years of industry experience designing custom mixed-signal silicon with a digital or analog focus.

Comprehensive understanding of both analog and digital design flows.

Experience modeling power & performance using Python models (or similar).

Experience communicating and presenting to highly cross-functional group of partners.

Experience working proactively with limited guidance.

Understanding of or direct experience with silicon fabrication and integration/packaging technologies

Keen interest in emerging AR/MR display technology

Preferred:

Preferred Qualifications:

Experience with array-based silicon architectures (e.g. SRAMs, image sensors, displays)

Exposure to III-V / Silicon integration processes.