Physical Verification Engineer

Physical Verification Engineer

The role requires expertise in physical design flows, verification, and various methodologies.

Job description:

Own and perform physical verification steps including DRC, LVS, ERC, ANT, DFM at the block, subsystem and fullchip level

Contribute to process flow and methodology for full chip assembly and tapeout signoff

Work with floorplan and physical design engineers to drive physical verification convergence

Perform technical physical evaluations of vendors, process nodes and IP

Contribute to design methodologies and automation scripts for physical verification steps

Requirements for this role:

3+ years of experience in physical design, verification, and various methodologies preferably in lower nodes (5nm/3nm).

Experience with Physical Verification tools (Calibre, Pegasus, PVS)

Experience with Physical Design tools like Innovus, Fusion Compiler

Experience in Python, Tcl, or Perl scripting