Senior Cyber FPGA Design Verification Engineer

Senior Cyber FPGA Design Verification Engineer

Dedham, MA

Up to $190,000 yearly

Direct Placement

Sign on Bonus - $3,000.00

RELOCATION ASSISTANCE AVAILABLE

As a Senior Cyber FPGA Design Verification Engineer, you’ll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products.

We encourage you to apply if you have any of these preferred skills or experiences: Experience with OVM / UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting languages; VHDL or similar hardware description languages.

What sets you apart:

Experience defining verification methodology for complex FPGAs.

Ability to analyze requirements, create test plan, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM

Familiarity with testing complex designs, code coverage, functional coverage, assertions.

Ability to work in a dynamic environment that includes working with changing needs and requirements.

FPGA/ASIC design experience is a plus.

Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus.

Team player who thrives in collaborative environments and revels in team success

Our Commitment to You:

An exciting career path with opportunities for continuous learning and development.

Research oriented work, alongside award winning teams developing practical solutions for our nation’s security

Flexible schedules with every other Friday off work, if desired (9/80 schedule)

Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more

Requirements:

Bachelor’s degree

Secret clearance

Willingness to travel occasionally

We are an EOE.

If interested, please contact

Thomas Masters

Ext. 212