Physical Design Methodology Engineer for High Performance / Low Power

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The Role:

Are you passionate about pushing the boundaries of power efficiency and high-frequency computing? As a part of our AMD physical design central methodology team, you can help define timing, power, and clocking methodologies for our next-generation, high-performance cores, graphics and machine intelligence chips. This team collaborates across AMD, working on projects ranging from low power APUs to the world's most powerful supercomputers.

The Person:

In this multi-functional role, you will have the opportunity to work across multiple divisions to drive physical design methodology optimizations across the entire physical design space (library/technology/flows/design).

We're looking for someone with excellent attention to detail, passion and curiosity to resolve complex issues while achieving amazing results!

We are looking for an experienced candidate with extensive experience in the following:

Key Responsibilities:

Responsibilities may include a subset of the following topics:

RTL (architecture) and PD co-development to identify bottlenecks

Drive IP physical implementation recipes from synthesis to route to achieve the best performance/watt

Drive budgeting, measurement, analysis and tracking of power-consumption

Establish global methodologies and best-known physical implementation recipes for optimal performance/watt across library/flow/Synthesis/P&R environment

Drive best practices for global/local clock distribution methodologies including skew/power/jitter trade-off's

Create guidelines on clocking/timing/power sign-off methodologies

Drive PVT corners/ frequency targets while considering various product performance modes and guard bands

Preferred Experience:

Expertise in these topics would be a plus:

CPU Physical design methodology

Design experience in sub-micron processes

Familiarity with CPU and or GPU architecture

Hands on experience with power-analysis and measurement tools like Prime Power and or Power-Artist

Experience with high performance clocking

STA methodologies for timing closure, OCV and other advanced statistical margining techniques

Proficiency in scripting languages such as Perl/Tcl/Python

Proficiency in data analysis and interpretation

Academic Credentials:

MS/PhD degree in Electrical Engineering is preferred

Mastery of logic, circuit design, and CAD tools for high-performance design is expected.

Location: Austin, TX

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.