Design Verification Engineer

We seek a Design Verification Engineer to support pre-silicon and post-silicon verification efforts in Austin, TX. This is a 1-year contract role requiring 3 days per week onsite.

Key Responsibilities:

Collaborate with design and architecture teams to define and execute verification plans for IP and full-chip environments.

Develop and maintain UVM/SystemVerilog testbenches, including stimulus drivers, BFMs, monitors, and checkers.

Create and simulate directed/random tests to validate low-power IP designs against specifications.

To ensure bug-free silicon, perform formal verification, coverage analysis, and RTL debugging.

Develop scripts (Python, Perl, C++) to automate verification flows and improve efficiency.

Support post-silicon validation by replicating and debugging issues in pre-silicon environments.

Verify power management techniques including clock gating, power gating, and voltage regulation.

Contribute to verification methodology improvements and tool development.

Required Skills & Experience:

Mandatory:

Hands-on experience with UVM and SystemVerilog for verification.

Proficiency in formal verification tools (e.g., JasperGold).

Knowledge of low-power design flows (UPF/CPF).

Strong scripting skills (Python, Perl, or C++).

Preferred:

Experience with analog-digital co-simulation.

Familiarity with emulation/FPGA modeling.

Background in x86/GPU power delivery or digital power management.

Knowledge of Design-for-Debug (DfD) techniques.

Additional Requirements:

Ability to work in a team environment with cross-functional stakeholders (designers, architects).

Strong analytical and problem-solving skills for silicon debug.