Design Verification Engineer - PCIe
Description:
What to work on industry defining technology in the high-speed domain? This role might be for you...
Roles & Responsibilities:
The primary responsibility of this position is to verify high-speed interface IO blocks, with a focus on modules that encompass various protocols such as PCIe, and CXL. This entails developing and setting up block-level environments.
The successful candidate will be responsible for constructing and reviewing comprehensive verification plans. This includes defining test methodologies, test cases, and coverage metrics. Furthermore, the candidate will execute test development, integration testing, and compliance testing using third-party verification IPs.
Key Qualifications:
7+ years of experience in design verification experience
Proficient in at least one of the following high-speed interface protocols: PCIe or CXL 2.0
Familiarity with SystemVerilog/UVM.
Minimum of 7 years of experience in ASIC verification.
Experience with commercial VIPs for these interfaces is advantageous.
Experience with high-speed interface bringup on HW emulator or silicon is advantageous.
Join a passionate team dedicated to transforming the future of accelerators. Competitive salary, comprehensive benefits, and professional development opportunities.