Digital Design Engineer

About the Role

As a Digital Design Engineer at The Six, you will be responsible for the design and bring-up of our memory PHY IP. You will be involved in the whole design process, from architecture to GDS realization. You will also be actively engaged with customers to ensure successful integration into their SOC.

Responsibilities and Duties

Architectural design including interface definition, power and frequency state logic, link training algorithm, phase tracking algorithm, PLL and DLL calibration, data path optimization and DFT

Implementation of PHY and Testchip RTL logic in Verilog

Functional modeling of PHY custom circuits in Verilog

Design specification for verification team and external customer

Review test plan and verification environment

Participation in testplan development

Testchip and PHY bring-up flow development

Customer integration and bring-up support

Requirements

Bachelor/Master in Electrical or Computer Engineering

Extensive RTL design experience in Verilog/VHDL

Deep understanding of timing constraints and clock domain crossing (CDC)

Knowledge of full ASIC design flow including synthesis, place and route, scan insertion, etc

Experience with design or validation of memory interfaces such DDR, LPDDR, HBM and GDDR

Proficient in scripting languages (Perl, Python, Tcl, etc)

TSS is looking to hire an exceptional Digital Design Engineer to join our team in Markham, Ontario.If you love to work and grow in a fast-paced environment where you can innovate and truly enjoy your work, please send your resume to and include the name of the position in the subject line.