FPGA Verification Engineer (Contract)
Description:
Employment Type: CONTRACT
The Client is looking for Citizens/GC.
JOB DESCRIPTION
Join our team as an FPGA Verification Engineer and play a crucial role in supporting FPGA debug, simulation, and testing activities for existing platforms. Your contributions will ensure the success of defined features and escalations.
Main Responsibilities:
Assist in FPGA debug, simulation, and testing activities for current platforms.
Create updated RTL designs for identified issues and conduct block-level simulations utilizing UVMF.
Generate test cases for UVMF.
Support mono and functional integration through customer delivery.
Update and generate necessary documentation.
Essential Skills:
Proficient in writing and updating VHDL RTL.
Strong expertise in FPGA design using VHDL, along with module and multi-module verification using System Verilog.
Experience with automated self-checking test bench verification in UVM (QuestaSim).
Ability to conduct timing simulations, post-route simulations, and static timing analysis.
In-depth experience with hardware development tools and IDEs for Xilinx devices (e.g., Vivado).
Familiarity with FPGA concepts, architectures, and protocols (SoC, bus topology, CDC, PCIe, TSN, UART, SPI, AXI, PTP, SRIO, etc.).
Preferred Skills:
Experience with Siemens UVMF.
Experience with Xilinx Zynq UltraScale+ MPSoC.
Knowledge of Altera development tools is a plus.
Soft Skills:
Adept at reading and interpreting data, information, and documents.
Creative at solving complex problems.
Proven track record of completing assignments with precision and high quality.
Ability to perform successfully in a dynamic environment with changing workloads.
Professional and effective communication skills.
Capability to establish and maintain cooperative working relationships with team members.
Best Regards,
Bini Skaria,
DRS IT Solutions Inc,
28175 Haggerty Road,
Novi, MI 48377
An E-Verified Company
Certified Women Business Enterprise (WBENC) Certified Women Owned Small Business (WOSB)