System IP Design Verification Engineer

Job Title: Senior Staff System IP Design Verification Contractor

Vertical: Technical

Locations:

3900 N Capital of Texas Hwy, Austin, TX, USA

3655 N 1st St, San Jose, CA, USA

Duration: 6-month assignment

Reports To: System IP Verification Lead

Job Type: Contract

Experience Level: Senior (12+ years preferred) Position Overview

Samsung is a global leader in semiconductor innovation, driving progress in memory, LCD, and System LSI technologies. As part of our expanding investment in design innovation-including a $17B commitment to the new 3nm Fab in Texas-we are actively growing our design capabilities across GPU, SoC Architecture, and System IP.

We are seeking a Senior Staff System IP Design Verification Contractor to join our System IP team in either Austin, TX (SARC) or San Jose, CA (ACL). This is a hands-on, technical individual contributor role focused on the functional verification of coherent interconnects, caches, and memory controllers.

Key Responsibilities

Architect and develop reusable and scalable testbenches from scratch

Lead and implement best practices, methodologies, and automation to boost verification efficiency

Create and execute detailed test plans, present strategies to stakeholders, and own feature-level execution

Collaborate with designers to resolve spec and implementation issues

Build complete UVM/SystemVerilog environments, including stimulus, checkers, monitors

Develop and debug assertions, covergroups, and constraints

Conduct GLS (Gate-Level Simulation), identify and debug timing violations

Perform code/functional coverage analysis and execute gap closure

Partner with SoC, physical design, and performance verification teams for co-simulation, power-aware (UPF) bring-up, and system-level debug

Assist in post-silicon bring-up and failure root cause analysis

Work closely with internal cross-functional teams for regression debug, vector generation, and feature verification Minimum Qualifications

PhD/MS/BS in Electrical or Computer Engineering

12+ years of experience in design verification, with significant hands-on UVM/SystemVerilog coding and debug

At least 5 years of GLS experience, with deep knowledge of gate-level simulations and timing closure

Strong knowledge of ARM protocols (e.g., CHI, AXI, ACE-Lite, APB)

Familiar with Git, Unix, and scripting (Perl, Python)

Proven ability to work across design and verification teams, driving timely closure of bugs

Excellent communication, documentation, and presentation skills Preferred Qualifications

Combined experience in coherent interconnects, cache systems, and LPDDR memory controllers

Familiarity with formal verification tools and methodologies

Knowledge of power-aware flows (UPF)

Experience supporting SoC-level integration and debug