CoWos Packing Engineer

Responsibilities

Develop and optimize CoWoS packaging processes to improve chip performance, power, and reliability

Collaborate with design, test, and manufacturing teams for seamless chip-package integration

Drive failure analysis and yield improvements across packaging flows

Ensure CoWoS packaging meets thermal, mechanical, and electrical performance requirements

Support new product introduction (NPI), from prototyping to high-volume manufacturing

Work closely with foundry and OSAT partners (e.g., TSMC, ASE) on process qualification and production ramp-up Qualifications

Bachelor's or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field

Minimum 15 years Hands-on experience in advanced semiconductor packaging and interconnect processes

Hands-on experience in advanced semiconductor packaging and interconnect processes

Familiarity with CoWoS, InFO, Fan-Out, and 2.5D/3D integration technologies

Strong understanding of thermal management, reliability testing, and signal/power integrity challenges

Excellent analytical and problem-solving skills with a proactive, collaborative approach

Experience working with TSMC and leading OSATs