Physical Design Engineer - STA

Summary

Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Static Timing Analysis Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers.

We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, but with a special focus on static timing analysis: developing and debugging constraints, specifying timing ECOs, and driving overall timing convergence on a complex, large die size, high-speed networking device.

Roles and Responsibilities

Perform STA (static timing analysis) at block/full-chip level

Specify timing ECOs either manually or via a tool-generated flow

Perform noise analysis at the block/full-chip level

Develop and debug timing constraints

Define and implement MCMM (multi corner, multi-mode) timing closure methodology

Drive and implement hierarchical timing methodologies to close timing at full-chip Skills/Qualifications:

Proficient in STA tools like Tempus, Tweaker, and PrimeTime

Proficient in programming languages like Tcl, python, etc.

Experience with timing constraint verification tools, such as TimeVision or FishTail, is a plus

Experience defining and developing timing closure methodologies in 7nm, 5nm, and/or 3nm

Previous experience integrating timing constraints for high-speed IO such as SerDes and/or DDR

Strong understanding of LVF/OCV variation methodologies and their implementation

Knowledge of timing convergence in multi-voltage scenarios

Working knowledge using timing derates and implementing timing derates into the flows

Minimum BSEE/CE + 10 years or MSEE/CE + 5 years experience.

Proven track record of execution on products which have shipped in high-volume.

About Us

Enfabrica is on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, Enfabrica sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, Enfabrica is unleashing the revolution in next-gen computing fabrics.