Senior Research And Development Engineer

Principal R&D Engineer – IC Design (Bay Area, CA)

Are you passionate about pushing the boundaries of chip and package design? A top-tier team developing next-gen network switches for enterprise and mega-scale data centers is seeking an experienced R&D Engineer with a focus on advanced interposer technologies.

In this role, you will:

Design/layout cutting edge CoWos 2.5D, 3D interposer, starting with custom routing for high-speed interfaces, bump map design, routing and physical verification and tapeout to foundries

Collaborate with packaging, signal integrity, and foundry teams to meet design and physical requirements

We're looking for someone with:

10+ years of experience in interposer and advanced packaging design

Deep knowledge of tools like Cadence (Innovus & Integrity), Synopsys 3DIC Compiler, and Mentor Graphics Calibre

Strong understanding of TSVs, micro-bumps, solder bumps, and interconnect technologies

Strong scripting skills (Python, Tcl, SKILL) for automation and flow customization

Familiarity with semiconductor fabrication processes and 3DBlox is a plus

Compensation:

Total package ranges from $400K to $500K, depending on experience and fit

Location:

Onsite in the Bay Area

This is a great opportunity for someone who thrives in a cross-functional, high-performance environment and enjoys taking designs from concept through to tapeout.

If this sounds like a fit—or you know someone who might be—let’s connect. Feel free to message me or drop a comment below.