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RTL Design Engineer

Company:
Canvendor
Location:
Dallas, TX, 75215
Posted:
May 24, 2025
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Description:

We do have an RTL Engineer role in Dallas, TX (Onsite). Please find the Job Description below and kindly respond back with your updated resume.

Job Title: RTL Engineer

Job Location: Dallas, TX (Onsite)

Duration: 12+ Months

Job Description:

We are currently seeking a highly skilled RTL/ASIC Design Engineer to join our dynamic team. If you possess hands-on experience and expert-level knowledge in RTL design, SoC integration of ARM core-based designs, and a deep understanding of Verilog/VHDL, we invite you to apply.

Responsibilities:

Execute RTL design and coding with expert-level proficiency

Integrate ARM core-based designs into SoCs, ensuring seamless compatibility

Work with AMBA Bus protocols, including AXI, AHB, APB

Conduct Lint and CDC analysis for design robustness

Utilize FPGA-based designs or FPGA prototyping for development

Apply in-depth knowledge of Verilog/VHDL and ARM SoC architecture

Perform ASIC synthesis and Static Timing Analysis at an expert level

Execute equivalency checking to ensure design accuracy

Collaborate with cross-functional teams to achieve project milestones

Participate in debugging sessions, provide insights, and maintain effective communication within the team

Requirements/Skills:

Hands-on experience and expert-level knowledge in RTL design and coding

Expertise in SoC integration of ARM core-based designs

Experience with AMBA Bus protocols (AXI, AHB, APB)

Hands-on experience with Lint and CDC analysis

Experience with FPGA-based designs or FPGA prototyping

In-depth understanding of Verilog/VHDL and ARM SoC architecture

Hands-on experience and expert-level knowledge in ASIC Synthesis

Hands-on experience and expert-level knowledge in Static Timing Analysis

Experience in equivalency checking

Preferred Skills:

Experience in Ethernet, PCIe

Experience in the networking domain

Proficiency in scripting languages such as PERL, TCL, Python

Experience with Cadence/Synopsys toolsets

Apply