System Validation Engineer

Title: Validation Engineer – Intermediate

Duration: 6+months

Location: Santa Clara, CA (Hybrid)

Job Duties:

In this role, this engineer will be part of a highly technical team that develops test plans, completes functional & electrical validation, & debugs issues for memory controller, NOC & other silicon interface features.

Executes electrical & functional test plans for client processors using hardware & software validation tools, oscilloscopes, & logic analyzers.

Debug of electrical & functional issues for new processors. Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.

Experience And Education:

Bachelors in Electrical Engineering or Computer Engineering with 3-5 years of related experience; or Masters plus at least 2 years directly related experience (an advanced degree will be considered a plus).

Requires experience and demonstrated technical expertise in the development & execution of platform level functional test plans.

Platform level electrical characterization experience with processor I/O interfaces is considered, preferred.

Requires experience and demonstrated technical expertise in the debug of processor & PC platform I/O interfaces.

Demonstrated experience with or knowledge using oscilloscopes, good scripting skills using Tcl or Python, and MS Windows and Office applications.

Requires good written and oral communication skills.

Demonstrate the ability to communicate with a variety of engineering disciplines and management.