Senior Full Custom Silicon Engineering Manager, Raxium

Minimum qualifications:

Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.

15 years of experience in full custom SOC design, or 10 years with an advanced degree.

3 years of experience in people management.

Experience supporting tape-outs of analog and mixed-signal circuits.

Preferred qualifications:

Master’s degree or PhD in Electrical Engineering or related field.

Experience in Silicon Memory Implementation like Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), etc.

Experience in patented technology.

Experience publications in relevant conferences or journals.

Excellent communication and cross-functional collaboration skills.

About the job

We are seeking a highly skilled and experienced Senior Full Custom Silicon Engineering Manager with Customer Owned Tooling (COT) and complementary metal-oxide semiconductor (CMOS) expertise to join our dynamic team and develop the next generation of our silicon for MicroLED-based microdisplay CMOS backplane.

In this role, you will be responsible for the design, simulation, and layout of high-performance analog and mixed-signal circuits in advanced CMOS technologies, managing design groups situated in multiple geographic locations (India and USA). You will play a key role in the development of next-generation products, contributing to all phases of the design process from concept to production.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $227,000-$320,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Lead end-to-end full chip integration, encompassing analog IP specifications, seamless integration, and extensive design and simulation activities for complex analog and mixed-signal circuits.

Drive the development and integration of large, full-custom Pixel Array IP, including specialized MicroLED drivers for individual pixel diodes.

Direct the complete physical design flow, including Register Transfer Level (RTL), Analog Mixed Signal (AMS), Memory Built In Self Test (MBIST), Built In Self Repair (BISR), Automatic Test Pattern Generation (ATPG), Place and Route (P&R), Layout Vs Schematic (LVS), Design Rules Check (DRC), Electrical Rule Check (ERC), Electro Migration (EM), Dynamic/Static Voltage Drop (IR) and Design For Test (DFT).

Manage and mentor high-performing Physical Design (PD), Design and Verification (DV), and DFT teams based in Bangalore, India.

Collaborate closely with architecture and software teams, ensuring seamless hardware-software co-design and optimize system performance.