Senior FPGA Design Verification Engineer

Job Description

Our global, technology solutions, products and services client has asked The Maven Group to help find a talented FPGA Design Verification Engineer for one of their office locations, just south of Boston, MA. This role requires an active Secret Clearance or higher.

This role requires 100% on-site work. A full relocation package can be provided if needed. Due to the nature of these roles ONLY US Citizens can be considered. The chosen candidate should expect competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs (including on-site gym) and more.

The chosen Senior Cyber FPGA Design Verification Engineer will be working with a team focusing on developing important Cybersecurity devices. These devices are at the cutting edge of Cybersecurity and high-speed data. You'll be part of a team responsible for product design from system architecture through product release.

This project requires an Active Secret Clearance or higher.

You should apply if you have any of these preferred skills or experiences:

Experience with OVM / UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting languages; VHDL or similar hardware description languages.

What we'd like to see:

Experience defining verification methodology for complex FPGAs.

Ability to analyze requirements, create test plan, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM

Familiarity with testing complex designs, code coverage, functional coverage, assertions.

Ability to work in a dynamic environment that includes working with changing needs and requirements.

FPGA/ASIC design experience is a plus.

Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus.

Active Secret Clearance

Full-time