Lead Digital Design Engineer (RTL)

SBT is the exclusive retained executive search firm for this position

This early-stage startup is looking to bring on a Lead Digital Design Engineer who will be responsible for leading the RTL development and microarchitecture design of high-performance AI inference accelerators. This role will own the RTL design and microarchitecture development, ensuring scalability, efficiency, and performance. The ideal candidate will collaborate with various teams to bring the ASIC from concept to tape out.

Role

Develop and lead the design of high-performance AI inference ASICs, focusing on scalability, efficiency, and performance

Design and architect key blocks, including compute cores, memory subsystems, and high-speed interfaces, to ensure optimal functionality and integration

Optimize the design for power, performance, and area (PPA) by implementing innovative techniques such as clock gating, power domains, and dynamic voltage and frequency scaling (DVFS)

Collaborate with cross-functional teams to develop hardware-software co-design strategies for AI model execution, ensuring seamless integration and optimal performance

Drive the development of front-end design methodologies, including synthesis, static timing analysis, linting, and power analysis, to ensure efficient and reliable design flows

Work closely with verification teams to develop test plans, coverage goals, and verification strategies for block- and system-level validation, ensuring robust and reliable design verification

Qualifications

Master's or PhD degree in Electrical Engineering (or relevant engineering field)

10+ years of experience in digital design for high-performance ASICs

Proven track record in leading digital design teams through multiple ASIC tapeouts

AI/ML acceleration architectures, tensor cores, matrix multipliers, and high-throughput data processing