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ASIC Designer

Company:
TRG
Location:
Santa Barbara, CA, 93190
Posted:
May 15, 2025
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Description:

RESPONSIBILITIES

Establish block level specifications based on system requirements

Design, simulate, implement and test analog/mixed-signal CMOS transistor level circuit designs for LIDAR application.

Guide physical design team to establish optimal layout and perform post-layout analysis.

Support chip level validation, test development, lab characterization, and transition to mass production.

Technology nodes range from 22 nm - 180 nm.

REQUIREMENTS

Bachelorâ?s degree in Electrical Engineering, Physics or related discipline.

Minimum 5 years of experience in CMOS analog/mixed-signal design.

Experienced in ASIC Design

Understanding of key challenges in sensor design (mitigation of signal and power supply crosstalk)

Familiarity with standard EDA tool suites for custom circuit design (Cadence, Mentor, Synopsys)

Good communication skills and successful in a team-oriented environment.

PREFERRED REQUIREMENTS

Automotive experience

Familiarity with digital design flow and tools

Familiarity with optical receivers

IMMEDIATE BENEFITS

Paid Time Off

Tuition and Employee Discounts

Annual Bonus

Employer 401(k) Match

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