Sr ASIC/FPGA VHDL Design Engineer

Title: Senior ASIC/FPGA VHDL Design Engineer

Location: Camden, NJ

Job Type: FTE/Permanent

Schedule: 9/80 Regular with every other Friday off

Position Overview:

Reporting to the Engineering Manager, the Senior Member of Engineering Staff (SMES) will be an integral part of the ASIC/FPGA design team. The role involves delivering FPGA/ASIC designs for high-speed applications, including the development of crypto architectures on ASICs and FPGAs. The position will require hands-on design and debugging of high-performance systems, utilizing various protocols such as Ethernet and TCP/IP. The organization utilizes advanced EDA tools and methodologies, including Synopsys, Xilinx, Client, and Microchip EDA, with HLS, Mentor EDA, and associated tools.

Key Responsibilities:

Derive engineering specifications from system requirements and develop detailed architecture.

Design RTL and/or HLS (C++ to RTL) and ensure RTL quality through CDC, RDC, Formal, and Lint.

Generate comprehensive test plans.

Perform module-level verification, synthesis/STA, lab debugging, and software-driven validation.

Support silicon/FPGA bring-up, characterization, and production ramp-up.

Provide engineering support for production and collateral development. Required Qualifications:

Bachelor's or Master's degree in Electrical Engineering or a related field.

5+ years of experience in developing, implementing, and verifying high-performance ASIC/FPGA products.

Experience with mapping algorithms and standards (e.g., Ethernet, TCP/IP, AXI) to hardware and understanding architecture/system design tradeoffs.

Proficiency in CDC, RDC, and formal EDA tools.

Expertise in VHDL is required.

Proficient in synthesis and place-and-route tools (e.g., Synopsys Synplify, Vivado).

Strong debugging and analytical skills for logic and board-level design.

Experience with project leadership and engineering validation methodologies. Preferred Qualifications:

Proficiency in C++ (Object-Oriented Programming).

Experience with Xilinx MPSOC design, including SDKs and BSPs for bare metal/PetaLinux OS.

Knowledge of protocols such as PCIe, NVMe, and USB.

Experience with High-Level Synthesis tools like Xilinx Vivado HLS or Mentor Calypto. Skills and Certifications:

Proficiency in VHDL.

Strong knowledge of EDA tools and formal verification methods.