Principal Analog Mixed Signal ASIC Layout Engineer

Overview:

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit

Job Description Summary: We are seeking a talented and motivated individual to join the analog mixed signal (AMS) ASIC team at Draper. The physical silicon design group is responsible for creating complex analog layouts from schematics in collaboration with other members of our incredible team. These layouts are used in ASICs for national security, biomedical, and space applications. While we are seeking a principal level engineer, considerations will be made at all levels for particularly capable applicants. A successful candidate will assist ASIC development through creating custom analog layouts, floor planning entire chips, high level problem solving, and executing tape outs. Skills with organizing and leading other layout engineers is also highly valued.

The ideal applicant is fully capable of working independently and communicating effectively with team members across different disciplines as well as program management. The candidate must have an understanding of silicon processing and the effect on circuit performance. Comprehension of and the ability to communicate about basic analog circuits is also desired.

While hybrid or remote work may be available, this position will have mandatory on-site work.

Job Description:

Duties/Responsibilities

Design and simulate circuits at transistor-level to implement architecture and requirement specifications

Contribute to system-level design

Optimize hardware designs for performance, power, and cost

Evaluate the hardware feasibility of complex algorithms and requirements

Independently contribute to complex chip architectures and designs

Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements

Contribute to business development and proposal activities

Develop, document, and teach best practices to less experienced engineers

Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics, contribute to design-for-test development.

Perform other duties as assigned

Skills/Abilities

Proficiency in integrated circuit design

Understanding of integrated circuits, semiconductors, and general computer architecture

Ability to write detailed design specifications

Ability to lead multi-disciplinary technical teams

Excellent verbal and written communication skills

Excellent mathematical skills

Excellent organizational skills and attention to detail

Excellent time management skills with the proven ability to meet deadlines

Strong analytical and problem-solving skills

Ability to prioritize tasks

Demonstrate strong organization, planning, and time management skills to achieve program goals

Education

Requires a bachelor's degree in Engineering, or related field. Masters degree preferred.

Experience

Requires 7-10 years of experience with a bachelor's degree, or 5-10 years of experience with a master's degree in ASIC Hardware Engineering or related.

Preferred Qualifications:

Experience with low power circuit design

Experience with CMOS advanced nodes below 32nm

Experience with radiation-hardened electronics

Additional Job Description:

Experience with Cadence Virtuoso and Siemens Calibre tools.

High proficiency in implementing analog designs into full custom layout. PLLs, DACs/ADCs, high speed SerDes, bandgaps, ESD/IO, and more.

Ability to recognize layouts vulnerable to failure and ways to fix. ESD/LU, DFM, etc.

Fluent in layout effects and how circuit performance can be affected. NW proximity, length-of-diffusion, implant shadowing, EM/IR, self-heating, coupling capacitance, matching techniques, etc.

Significant experience with understanding and debugging DRC, LVS, PM, and other physical verification tools and methodologies.

Ability to be the sole layout resource for an entire chip, from transistor level layout to chip level integration and tape out.

Experience with chip level/top down floor planning, delegating work to other layout resources in a small team, and communicating technical information across different disciplines and experience levels.

Preferred experience with automated tools (Cadence ModGen/autorouter/EAD, Innovus, etc), and methods for transferring data between domains (abstract/LEF).

Able to motivate themselves and operate independently.

Ability to mentor others and willingness to be mentored.

Experience operating in a Linux environment. Preferred experience with scripting (SKILL, SVRF, tcl).

Experience with FinFET processes, 22nm to 7nm and below.

Applicants selected for this position will be required to obtain and maintain a government security clearance

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Job Location - City: Cambridge

Job Location - State: Massachusetts

Job Location - Postal Code: 02139-3563

Draper is committed to creating an inclusive environment. We understand the value of inclusivity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, national origin, veteran status, or genetic information. Draper is committed to providing access, equal opportunity, and reasonable accommodation for individuals with disabilities in employment, its services, programs, and activities. To request reasonable accommodation, please contact .