RTL IP/Logic Design Engineers / Design Architect Leads

RTL IP/Logic Design Engineers / Design Architect Leads

This position is for IP Design Engineer Lead/manager role at Samsung Semiconductor India Bangalore, where you will be involved in RTL design, synthesis and verification of various complex IP modules of SSD/Flash storage products. You will be associated in the design development life cycle to support spec to tape-out defined by specific assignment. You will also be responsible for providing technical inputs or guidance to improve and adhere to hardware development and quality processes necessary to ensure the design consistently meets the required functionality, re-usability, reliability, performance and power targets to ensure Samsung SSDs meet their design targets

Education & ExperienceBachelors / Master’s Degree in Electronics/ Electrical Engineering from reputed universities

5 - 18 years of digital logic design experience.

General DescriptionKey responsibilities includes (but not limited to): Architecture, Design and RTL development for storage controller IP's based on NVMe, UFS, and high speed peripheral bus standards such as PCIe and CXL.Technically lead various RTL modules developmentInterfacing with cross functional teams like Verification, Validation and FW.Ensuring quality of design using Lint and CDC checks.Synthesis, Area and power optimization.Developing the timing constraints ( SDC) and ECO scripts.

Necessary Skills/AttributesWorking experience in complex IP Design.Experience in designing and RTL coding using Verilog /System Verilog/VHDL and verifying design with module level testbench or with formal techniques.Design QC using lint/CDC/DFT.Compile, elaboration and simulations for QC. Experience with Xcellium/VCS, Verdi, and Spyglass.Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management.Experience in writing functional design doc and/or functional specifications.Experience in synthesis using Synopsys Design Compiler (DC) and developing timing constraints (SDC) and Timing analysis. Experience in low power design methodologies and related power estimations, power measurements during implementation.Experience in usage of formal verification tools like Jasper-FPV, SEC while implementing designs will be big plus. Experience in developing/understanding of ECOsWorking experience in teams with collaboration of effort between Verification, Validation, Physical Design and DFT Additional Qualifications (preferred)Experience in RTL integration tools like Magillem is added advantage.Working experience in High speed serial protocols like PCIe, SAS, NVMe, Fabrics, UFS Familiarity with FPGA based development is additional plus.Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip ) and ARM CPU Architectures would be added advantage.Team player, can-do attitude is desirable. Passion for working on cutting edge technologies, eager to learn and ability to be analyze/debug designs are highly desirable.

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