SOC Engineering, Principal Engineer

Requisition Number

50038BR

Job Description and Requirements

At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you.

Job Description and Requirements

The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies.

As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors.

Responsibilities

Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities.

Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities.

Lead team of engineers to perform various pre-silicon static verification activities on IPs/Subsystems.

Understand the design/architecture and lead the team to develop timing constraints for synthesis and timing.

Work with peers to improve methodology and improve execution efficiency.

Ramp-up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers.

Work with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tool and IP solutions.

Setup flows and methodologies to enable quick setup for RTL Quality checks, Synthesis and Formality.

Train the team in design concepts and root-cause analysis.

Required

B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years’ experience in RTL Design and Verification.

Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC.

Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools.

Technical expertise in debugging and diagnosing violations and errors.

Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation.

Ability to lead a team to perform RTL Signoff on complex SoC/IP/Subsystem.

Experience with planning and managing various activities related to RTL Signoff and Design.

Strong understanding of design concepts, ASIC flows and stakeholders.

Good communication skills.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Business Title (Title for Job Posting)

RTL Design and Signoff Engineer, Principal Engineer

Job Category

Engineering

Job Subcategory

SOC Engineering

Hire Type

Employee