Senior Engineer, Physical Design Engineering

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible.

Position :Senior PD Engineer

ADI's Digital Business Unit (DBU) is looking for Senior PD Engineer for the development of complexmixed Signal SoCs. These chips are manufactured in most leading edge process nodes and high speed clock rates.

These SoCs involve multiple processor cores andspeed signal processing hardware running at high speed.

Position Requirements

- BTech/MTech degree in Electrical/Electronics from a reputed institute with 4-8years of experience in the field of Digital place and route

-Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (16nm, 7nm etc).

- Hands on experience in handling the tapeout ofcomplex high speed SoC designs in cutting edge process technologies

- Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction

- Strong expertise in Static Timing analysis, constraint development and sign off.

-Innovate on the flows to meet the QoR targets and ensure predictability

- Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage.

- Being proficient in TCL, python etc.

External

Position :Senior PD Engineer

ADI is looking for Senior PD Engineer for the development of complexmixed Signal SoCs. These chips are manufactured in most leading-edge process nodes and high speed clock rates.

These SoCs involve multiple processor cores and speed signal processing hardware running at high speed..

Position Requirements

- BTech/MTech degree in Electrical/Electronics from a reputed institute with 4-8 years of experience in the field of Digital place and route

-Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (16nm, 7nm etc).

- Hands on experience in handling the tapeout ofcomplex high speed SoC designs in cutting edge process technologies

- Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction

- Strong expertise in Static Timing analysis, constraint development and sign off.

-Innovate on the flows to meet the QoR targets and ensure predictability

- Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage.

- Being proficient in TCL, Python etc.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

Full time