Senior Digital Design Engineer

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today's innovators stay Ahead of What's Possible.

Job Responsibilities:

Designkey digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs

Develop strong understanding of heterogenous processor cores & subsystems (A55/ M55/ M4/ U55/ RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements

Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc

Consolidate & curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces & peripherals

Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations

Build expertise on complex interfaces, peripherals & protocols such as DDR, Ethernet, eMMC/ SD, MIPI, Display Port, HDMI, PCIe, high speed D2D

Develop and maintain catalog of digital IPs to enable ease of information sharing to customers across different BUs

Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc

Establish evaluation flows for home-grown & 3rd party IPs for consistent benchmarking of evaluation

Position Requirements:

Minimum B.E. / B.Techdegree in Electrical/Electronics/Computer science

2 - 6 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog

Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions

Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality

Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis

Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis

Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically

Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus

Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus

Experience with end-to-end ASIC/ SoC product development & productization is very desirable

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

Full time