Design Engineer MM

Job Description

High Speed DDRx data path design engineer

Job Requirements:

deep understanding memory interface protocol [DDRx, LPDDRx, GDDRx, HBM, Serial Link]

DDRx high speed Data path design experience

deep understanding Latency control and clock domain crossing

deep understanding redundancy control scheme

deep understanding clock tree and timing requirement

deep understanding memory core operation

deep understanding timing / power budget regarding data path

deep understanding redundancy control scheme

need to closely working with layout engineers

Verilog verification expertise- required

HBM expertise- required

Rx/Tx/ODT/ZQ cal/ESD -required

Additional Plus to Application:

understanding Memory Core operation a big plus

understanding ECC/CRC/Parity a big plus

* understanding DLL/PLL/DCC a big plus

* full data path simulation environment setup and circuit/timing verification is a plus

scripting language experience preferred

E04JI80240jb402vosi