Senior Engineer, Digital Design

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $12 billion in FY22 and approximately 25,000 people globally working alongside 125,000 global customers, ADI ensures today’s innovators stay Ahead of What’s Possible.

Job Responsibilities:

Work closely with the Architecture team to develop detailed specification, uArch and development plans,

Design key digital blocks such as accelerators/ datapath IP in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs

Develop strong understanding of heterogenous processor cores & subsystems (ARM / RISC-V/ DSP core, and associated infrastructure such as caches, interconnect fabric, GIC, DMA, MMU, Coresight Debug & Trace, TZC, SMPU, SPU) and their integration requirements

Develop User Guides for RTL Integration, Synthesis, Lint/CDC waivers, DFT, PnR, Programming Sequence, characterization etc.

Evaluate 3rd party IPs on Power/ Performance/ Area (PPA) and other key qualitative aspects such as design quality, Design For Testability, robustness of Design Verification (DV) practice, ease of integration and make recommendations.

Provide technical leadership and guidance to small teams of Micro-architects/RTL developers working on an SoC

Work closely with the verification team for vPlan reviews and for complex debugs to resolve verification failures.

Participate in design specification, micro architecture and verification sign off reviews.

Improve flows and methodologies to streamline IP development and integration

Build (including recruiting and interviewing) development teams

Position Requirements:

Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science

5 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog

Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions

Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality

Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis

Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis

Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically

Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus

Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus

Experience with end-to-end ASIC/ SoC product development & productization is very desirable

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days

R241147