Pre-Silicon Validation Engineer - System Verilog

Job Title : Pre-Silicon Validation Engineer Job Description : Validation Planning : - Collaborate with design and architecture teams to define validation requirements and develop detailed validation plans for complex semiconductor designs.

Testbench Development : - Design and develop scalable and reusable validation testbenches using System Verilog and UVM methodology to verify functionality and performance requirements.

Testcase Development : - Create testcases based on architectural specifications, functional requirements, and design intent to cover all aspects of design functionality.

Simulation : - Execute validation tests using RTL simulation tools (e.g., Cadence Incisive, Synopsys VCS) to verify design functionality, timing, and power requirements.

Emulation : - Utilize emulation platforms (e.g., Cadence Palladium, Mentor Veloce) to perform acceleration and in-circuit emulation (ICE) for faster validation of large-scale designs.

(ref:hirist.tech)