RTL Design Engineer - Verilog/AMBA

Our leading clients provide end-to-end support for the semiconductor industry.

They are looking for RTL Design to be based at Bangalore with the following skills: - Total 4 - 10 years of experience in RTL Design and coding experience in Verilog/VHDL - Must have strong understanding of Multi-processor and cache designs - Must have knowledge on various ARM AMBA protocols (e.g AXI, AHB etc) as well as cache coherency protocols - Must have good knowledge on various tools viz Spyglass, 0-in, DC-Compiler, Prime time, PTPX, Power-Artist,LEC etc - Working knowledge of timing closure is a plus - Expertise in Perl, TCL language is a plus Notice Period : 30 days or serving 60 days or 90 Day notice period Education : BE/BTech, ME/MTech ( VLSI Domain ) (ref:hirist.tech)