Design Verification Engineer - System Verilog

Our client is one of the fastest growing semiconductor start-up company.

They use unique processes to provide the best talent to its client in timely fashion in Design Verification, Design For Test and Physical Design They are looking for Design Verification Engineer (SE / SSE) to be based at Noida / Bangalore / Hyderabad with the following : - Total 3 to 7 years of experience in Design Verification - Must have experience in creating Verification Plans for SOCs And IP Blocks - Must have experience With System Verilog, UVM Reuse Methodology - Experience With Advanced Verification Techniques Like Constrained Random Generation, Functional Coverage, Assertions And Formal Verifiers - Gate level simulation setup and debugging - Must have experience in creating Testbenches In SystemVerilog With UVM methodology - Utilize Advanced Verification Techniques - Write Tools And Scripts In Perl And Other Script Languages To Enhance The Verification Process (ref:hirist.tech)