Job Description
Support customer’s design through all phases of ASIC execution.
Ensure designs meet product performance requirements
Contribute to microarchitecture, RTL design, synthesis, and timing closure.
Work effectively with internal teams, including verification team and physical design team.
The ideal candidate will possess the following qualifications:
Bachelor’s Degree in EE or similar degree.
5+ years of Front-End ASIC Design experience
4+ years of Microarchitecture experience
Hands-on ASIC front-end design, ideally in design services environments (product backgrounds acceptable).
Preferred:
Micro-architecture at module/sub-system/chip-level
Digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings
Integration of IPs/modules/sub-systems designed by internal/external teams
Experience using AMBA bus protocols
System Verilog experience
Lint and CDC execution and analysis
writing timing constraints and timing analysis
Technical document writing skill
Desired:
Experience in at least few of these:
CPU (preferably, ARM), or GPU, or DSP
low-power design and verification peripheral interfaces such as CSI, I3C, USB, PCIe; FPGA