Engineering (Senior Design Validation Engineer)

Seeking a highly motivated and innovative Digital Verification Engineer with exceptional theoretical and practical background in high-speed data recovery circuits.

Working as part of a highly experienced mixed-signal design team, you will be involved in verifying current and next generation products.

The position offers an excellent opportunity to work with digital and mixed signal design engineers accountable for delivering high-end mixed-signal designs.

Designing and writing constrained-random SystemVerilog testbenches using a UVM; Writing SystemVerilog assertions; Writing functional coverage; Bug Tracking using Software tools such as Jira; Code coverage Analysis; Preferred MSEE with at least 5 years of digital design and verification industry experience Must have hands-on experience in writing complex testcases in Verilog and System Verilog using UVM Knowledgeable on High-speed Digital & Mixed-signal Design All to help customers integrate more capabilities.

Meet unique performance, power, and size requirements of their target applications.

And get differentiated products to market quickly with reduced risk.

At Synopsys, we’re at the heart of the innovations that change the way we work and play.

Self-driving cars.

Artificial Intelligence.

And we’re powering it all with the world’s most advanced technologies for chip design and software security.

If you share our passion for innovation, we want to meet you.