Design Verification Engineer
Description:
Title: Design Verification Engineer
Duration: Full Time
Location: Hyderabad
Experience: 4
Description:
1.Experience in Verification of IP/SOC/Design
2.Experience in UVM/SV/ test bench development
3.Candidates with CPU-Core, Peripherals, Low Power Verification or Modem domain, debug skills, DV Integration are preferred.
4.Preferably with exposure to Power Aware/GLS, RISC-V processor
5. Protocols experience - PCIe/CXL/UCIe/DDR/Ethernet
6. In addition Formal, Assertions, Coverage etc, Netlist simulation experience
Expertise in SV-UVM, Testbench development from scratch