Embedded DSP Engineer

Reality Labs (RL) focuses on connecting people through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of these products require custom silicon.

The Silicon team is driving the state of the art forward with breakthroughs in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body.

We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, to firmware, and algorithms.

We are seeking an Embedded DSP Engineer who is excited about introducing groundbreaking capabilities in the fields of computer vision (CV), machine learning (ML), and imaging (ISP), Audio, Graphics and Display, through efficient implementation of algorithms on custom DSPs, and HW/SW partitioning and co-design of complex embedded algorithms into custom DSP + HW accelerators.

The successful candidate will be required to optimize kernels and libraries from high to low-level coding for current and future in-house heterogeneous compute platforms across custom DSPs and CPUs, or other ISA programmable cores (e.g.

Gfx). They will also have the opportunity to contribute in defining architectural requirements and ISA by working with multidisciplinary teams and providing detailed design specifications of such compute platforms.

Responsibilities:

Embedded DSP Engineer Responsibilities:

Code CV, ML, Imaging, Graphics, Audio algorithms on customized processors, and accelerators in C and/or C++ for performance, latency, power, and memory.

Perform low-level SW optimization at instruction level by loop optimization, vectorization, pipelining, data layout re-organization and cache/memory management.

Influence algorithm and application optimizations in the context of low-power edge devices, including memory footprint vs compute trade-offs, accuracy KPI vs power/latency.

Study state of the art algorithms in the field of CV, ML, Imaging, Audio to develop appropriate SW-HW partitioning.

Contribute in architecting custom processor and DSP ISA and uArch, for accelerating the target workloads.

As a DSP Embedded Engineer, step into and work closely with DSP HW architects, FW engineers, algorithm and application engineers across multiple disciplines (Vision, Audio, Graphics, ML).

Engage in building compute IP demos, and perform characterization and micro-benchmarking for design feedback on power and performance.

Qualification and experience:

Minimum Qualifications:

5+ years experience in CPU/DSP architecture, ISAs such as ARM, Tensilica, RISC-V, x86.

Experience with low-level SW optimization, loop optimization, data organization and caching.

Knowledge of ISA fundamental and experience programming in SIMD, VLIW, and/or Vector processors and/or custom ISA extensions.

Familiarity with embedded programming (IPC, synchronization, debug, scheduling, memory management), RTOS and their trade-offs and requirement.

Preferred:

Preferred Qualifications:

MS or PhD in EE/CS.

Experience with methods for partitioning a solution across hardware and software, and other multi-disciplinary boundaries in a system solution.

Knowledge or experience in the field of computer vision.

Knowledge or experience in audio and speech processing and pipeline (capture, render, codec).

Knowledge or experience in graphics and compute shading, and programming frameworks such as OpenCL, CUDA, OpenGL or Vulkan.

Knowledge or experience in image sensor processing (ISP).