Engineer II - VLSI (PD)

Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA analysis)

work on Functional DFT modes and constraints, Signal integrity, knowledge of de-rates (OCV, AOCV,POCV).

Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs

Experience with EDA Tools and Methodologies for STA, STA-based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating

Correlate results between STA and GLS with AMS

power management and UPF concepts at Synthesis/PnR/STA domains

What Youll Need:

Have 5+ years experience and will be reporting to Director - ASIC design.

Experience in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm)

Experience Timing Closure/ECOs on block level and chip level in a complex clocking environment including clear understand of clock domain crossings, Can work with Physical Design Teams.

Experience in Timing Closure/ECOs on block level and chip level in a highly including clear understand of clock domain crossings, Can work with Physical Design Teams.

Knowledge of Functional DFT modes and constraints, Signal integrity, knowledge of de-rates (OCV, AOCV,POCV).

Will need to be hands-on, defining constraints, margins based on tech nodes, incorporating feedback from the Analog Team in the SDCs

Experience with EDA Tools and Methodologies for STA, STA based ECO, Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating.

Correlate results between STA and GLS with AMS

Understanding of power management and UPF concepts at Synthesis/PnR/STA domains

Good scripting skills; experience in Tempus.

Full time