Senior Design Verification Engineer

About Us: Eximietas Design is a leading technology firm specializing in [VLSI/Cloud Computing/Cyber Security/AI/ML] solutions. With a commitment to innovation and excellence, we empower businesses to thrive in the dynamic digital landscape. Our success is fueled by the expertise of our engineering leadership team, drawn from industry giants such as Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun.

Job Overview: We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 10 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System On Chip designs.

Key Responsibilities:

Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.

Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM

Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.

Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.

Analyze and implement System Verilog assertions and coverage (code, toggle, functional).

Provide mentorship and technical guidance to junior verification engineers.

Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.

Ensure verification signoff criteria are met and documentation is comprehensive.

Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.

Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.

Experience with verification tools from Synopsys and Cadence, including VCS and Xsim.

Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.

Minimum Qualifications:

Bachelor degree in Computer Science, Electrical/Electronics Engineering, or related field. OR

Master degree in Computer Science, Electrical/Electronics Engineering, or related field. OR

PhD in Computer Science, Electrical/Electronics Engineering, or related field.

Min 5 years of hands-on experience in Design Verification.

Expertise in UVM (Universal Verification Methodology) and System Verilog.

Prior experience working on IP level and SOC level verification projects.

Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).

Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.

Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.

Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.

Proficiency in scripting languages such as shell, Makefile, and Perl.

Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.

C-Systemverilog handshake and writing C test cases for bootup verification.

Excellent problem-solving, analytical, and debugging skills.