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Unit/Chip/System Level Verification

Alten Calsoft Labs
Sunnyvale, California, United States
October 12, 2018


Position 2: Unit/Chip/System Level Verification

Skills/Experience Required\

Verilog knowledge – must have

C/C++ coding a must – must have

Strong scripting skills (Python, Ruby, TCL, Shell, Perl etc.) – must have at least one

Unit/Chip/Full system level ASIC Verification skills, and debug skills (using waveforms and Verdi source level debug ) – must have

Block/unit level verification skills using OVM/UVM – must have

Basic system level knowledge {CPU + caches + GPU + multi-media engines + Southbridge} must have

o System level knowledge/verification does not mean signal integrity checking, electrical checks, EMC checks, thermal checks, ATPG testing on a board, DFT/DFx testing, static timing analysis, lint checking

Excellent communication skills and demonstrate the desire to take on diverse challenges

Board level debug with logic analyzers, scopes a plus

Experience working with x86_64 architecture a plus

Experience working with PCI-Express a plus

Job Description

Core Responsibilities:

As a unit/chip/system verification engineer you will be involved in developing, debugging test environments as well as tests. You will also be involved in receiving and testing RTL and test bench drops from vendors and integrating these into Microsoft’s verification environment(s). Closely work with RTL/verification/design/SW engineers for debug and root-cause. Develop and debug related RTL models, assertions, collateral. Scripting and UVM coding as required.


Minimum BS (EE or CS) required with over 5 years relevant experience.


Engineer must work at our Sunnyvale facility, unless he/she has special needs.

What to look for in trying to match resumes:

? Experience working in AMD, Intel or other big SoC (system on chip) companies

? Experience writing “assembly language tests”, “assembly level” debug

? Experience with caches, coherency

? Experience with “concurrent tests”

? Experience working on board-level debug

? Experience unit level UVM verification

? Experience with scripting work (regression infrastructure)

? Debug experience (waveforms/Verdi)