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Design Verification Engineer

Company:
Semiconductor
Location:
San Diego, California, United States
Posted:
February 14, 2018
Description:

You will be responsible for building functional verification infrastructure, understanding the expected design functionality, developing test-plans as well as guiding the functional verification of complex SoCs by deploying OVM/UVM until coverage goals are achieved in order to insure the continued commercial success of our high quality products.

Minimum Qualifications:

• 5+ years of directly related industry experience in ASIC / SoC Verification -

• Expert knowledge in Object Oriented programming, data structures, and algorithms -

• In-depth knowledge of Digital Logic design techniques and principles. -

• Knowledge of wireless protocols such as Blutooth -

• Extensive architectural and verification knowledge of high performance bus protocols such as AHB and AXI. -

• Must have hands-on experience and expert level knowledge on HVL based verification flow (UVM, OVM), testbench automation, industry standard bug tracking, and regression mechanisms. -

• Must have expert understanding of code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions, and architectural performance testing to achieve coverage.

Preferred Qualifications: See minimum qualifications.

Education: Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's