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Formal Verification Engineer

Ryzen Solutions
Mountain View, California, 94043, United States
March 16, 2017

Formal Verification Engineer (3 positions)

General Description Vision:

Member of the formal verification of a new architecture GPU’s implementation for mobile cores.

Responsibilities Includes

Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the GPU pipeline and fixed function units

Closely interact with DV team and identify blocks/functionalities suitable for formal so that overall verification goals are met. Scope the required effort

Generate formal verification plan and execute it using Jasper. Provide support as and when required including during test planning and formal complexity resolution stage.

Experience Requirements:

Must have strong problem solving skills

Experience using formal verification (Jasper or VCFormal), as demonstrated by successful use of an IP or SOC is required

Some prior experience with simulation based environments like UVM/OVM/VMM

Good experience on verification planning and prior mentorship experience

Knowledge of computer architecture and pipelined designs is required

The qualified candidate will possess the following:

BSEE, preferably MSEE.

At least 3 years of industry experience, 1 of which in a formal verification role.

Proficient in Verilog and exposure to SVA

Hands on at least 1 formal verification tool (Jasper or VCFormal) – Jasper is preferred

Experience in scripting languages like Python, Perl, Unix shell or similar languages

Good verbal and written communication skills

Good team player