Elevate your engineering career as a Senior FPGA Design Engineer with a focus on Verilog and SystemVerilog. Lead complex design tasks while collaborating with multi-disciplinary teams to ensure high-performance solutions.
In this senior-level role, you will design and implement RTL for complex FPGA systems, translating high-level requirements into actionable designs. With expertise in FPGA tools like Xilinx Vivado and Intel Quartus, you will work on high-speed applications and drive the full design flow for optimal performance.
Key Responsibilities: • Design RTL with Verilog and SystemVerilog • Execute FPGA design flow including synthesis and timing closure • Collaborate with verification teams for correctness and coverage • Develop high-speed interfaces like PCIe and Ethernet • Support hardware bring-up and system integration activities
Requirements: • Proven experience in FPGA design and RTL coding • Strong knowledge of timing analysis and design optimization • Familiarity with FPGA toolchains for design workflows • Excellent debugging skills for hardware issues • Leadership experience in an engineering context
Drive high-performance FPGA projects and mentor peers in advanced engineering techniques. #J-18808-Ljbffr