Physical Design & Flow Methodology Engineer

Job Description

Responsibilities

PPA Optimization & Analysis

Drive PPA optimization (timing, area, leakage, dynamic power) across process nodes and hardware configurations

Apply low-power techniques (clock gating, multi-Vt, operand isolation) and tune synthesis/P&R to meet frequency and area targets

Characterize design space and build PPA models to support customer evaluations and pre-sales

Partner with RTL and architecture teams early to quantify trade-offs and influence design decisions

Reference Flow Development

Build and maintain scalable RTL-to-GDSII reference flows for Quadric soft IP

Ensure portability across process nodes with clear BKMs, SDC templates, floorplan scripts, and integration guidelines

Develop automation using TCL and Python; leverage AI tools (e.g., Claude, Copilot) to improve efficiency and repeatability

Qualify EDA tool updates and benchmark QoR before integrating into the flow

Customer Integration & Tapeout Support

Act as the primary PD point of contact for customers from evaluation through tapeout

Support adaptation of reference flows across process nodes, foundry PDKs, and customer environments

Debug and resolve implementation issues (timing, congestion, power, flow failures)

Support FAE and business teams with PPA feasibility studies

Collaboration & Documentation

Work closely with architecture, RTL, and software teams to meet PPA targets

Document methodologies, best practices, and process node bring-up guidelines

Ideal Candidate

BS/MS in Electrical Engineering, Computer Engineering, or related field

7+ years of ASIC or processor IP physical design experience focused on PPA optimization and flow development

Technical Skills

Hands-on experience with Synopsys or Cadence tools (synthesis, place & route, STA)

Experience with advanced nodes (16nm and below, FinFET); multi-node exposure preferred

Strong scripting skills in TCL and Python

Solid understanding of timing closure, congestion, power optimization, and MCMM analysis

Experience with low-power design techniques

Familiarity with AI-assisted coding tools (e.g., Claude, Copilot) for automation and productivity

Understanding of DFT concepts and their physical design implications

Nice to Have

Experience delivering soft IP to external customers or supporting SoC integration through tapeout

Background in AI accelerator, NPU, or DSP IP

Exposure to QoR tracking and large-scale synthesis/implementation runs

What’s on Offer

Opportunity to work on cutting-edge edge AI processor technology

High-ownership role with direct impact on PPA, product delivery, and customer success

Collaborative, low-ego engineering culture

Fast-paced environment with strong learning and growth potential