ASIC Engineering Technical Lead - W2

Job Title: ASIC Engineering Technical Lead - W2

Work Location & Reporting Address: San Jose, CA 95134

Minimum years of experience: 10+ years

Contract duration: Long-term

Job Details:

Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips · Design & implement robust and reusable RTL with CDC/RDC considerations · Spec comprehensive CDC/RDC check flows and work with CAD team to implement · Review and approve CDC/RDC constraints and waivers · Perform static glitch analysis Improve design with prevention of static glitch harzad

· Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design · RTL development skills and experiences · Solid understanding on CDC/RDC concepts and relevant design implementation · Experience on maintaining CDC/RDC flow and signing-off constraints and waivers · Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists

Preferred Qualifications

· Experiences on Static Timing Analysis

· Experiences on VCS simulation SVA (SystemVerilog Assertions)

Top 3 responsibilities you would expect the Subcon to shoulder and execute:

We are looking for a senior CDC Clock Domain Crossing Contractor based in the US. The contractor will work on ASIC DFT CDC constraints until our group can fill in the position. Interview will test understanding of CDC and Spyglass tool at a senior level. Contractor Requirements Skills Skill set Spyglass CDC VCSpyglass. CDCRDC knowledge Estimated rate 100 per hour Location Ideally able to badge into the Cisco Milpitas offices. Otherwise remote US PST