Design Verification Engineer

KEY RESPONSIBILITIES:

Lead Formal verification.

Create UVM/System Verilog based testbenches and tests.

Comprehend AMS, Firmware and design spec. Work with other functional leads to come up with a DV plan and execute the plan.

Define verification plan, and provide technical direction to execution teams

Make sure that design is bug free.

Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.

PREFERRED EXPERIENCE:

Formal verification expertise.

Firmware experience.

IO/PHY knowledge.

Excellent communication, management, and presentation skills.

ACADEMIC CREDENTIALS:

Bachelor's or Master's degree in Electronics.