| Resume alert | Resumes 31 - 40 of 55 |
Manager Support
Washington, DC
... Configuring and managing routing table Managing and configuring VIPs for XA, XM and Unified Gateway Configuring and Managing for STA and XML server Configuring virtual servers for load balancing Site redirections (protection and responder policy) ... - 2017 Jun 26
... Configuring and managing routing table Managing and configuring VIPs for XA, XM and Unified Gateway Configuring and Managing for STA and XML server Configuring virtual servers for load balancing Site redirections (protection and responder policy) ... - 2017 Jun 26
Design Engineer
Herndon, VA, 20170
... timing requirements.(Cadence SOC Encounter for placement and routing, Synopsys Design Compiler tools used for synthesis),Did STA using Synopsys Primetime to find out violating elements and optimized it’s transistor sizing to meet timing requirement. ... - 2016 Dec 15
... timing requirements.(Cadence SOC Encounter for placement and routing, Synopsys Design Compiler tools used for synthesis),Did STA using Synopsys Primetime to find out violating elements and optimized it’s transistor sizing to meet timing requirement. ... - 2016 Dec 15
Manager Engineering
Washington, DC
... Sta. Maria, Jr. *** **** ****** ******* ********** 98122 : 206-***-**** : mailto:acw24h@r.postjobfree.com@gmail.com Summary ** ***** ** ********** ** semiconductor back-end test manufacturing, product and test engineering Managed and directed ... - 2016 Oct 16
... Sta. Maria, Jr. *** **** ****** ******* ********** 98122 : 206-***-**** : mailto:acw24h@r.postjobfree.com@gmail.com Summary ** ***** ** ********** ** semiconductor back-end test manufacturing, product and test engineering Managed and directed ... - 2016 Oct 16
Design Computer Science
Rockville, MD
... II, Xilinx Vivado, Conformal ASIC Design flow: RTL Design/coding, Low Power Design, Synthesis, Verification, ATPG, DFT, STA, DRC, LVS Operating Systems: Windows, Linux Coursework: High Level VLSI Design Methodology, VLSI Design and Simulation, ... - 2016 Sep 23
... II, Xilinx Vivado, Conformal ASIC Design flow: RTL Design/coding, Low Power Design, Synthesis, Verification, ATPG, DFT, STA, DRC, LVS Operating Systems: Windows, Linux Coursework: High Level VLSI Design Methodology, VLSI Design and Simulation, ... - 2016 Sep 23
Network Engineer
Sterling, VA
... - Network Monitoring: Experience with monitoring port traffic and errors, notification of device sta- tus, and capturing traffic using PRTG and Wireshark. Chris Hendrickson 703-***-**** acsvdx@r.postjobfree.com - Network Troubleshooting: Work on ... - 2015 Dec 21
... - Network Monitoring: Experience with monitoring port traffic and errors, notification of device sta- tus, and capturing traffic using PRTG and Wireshark. Chris Hendrickson 703-***-**** acsvdx@r.postjobfree.com - Network Troubleshooting: Work on ... - 2015 Dec 21
Design Project
Oakton, VA
... Parallel Processors, HPC, FLOPS ASIC Design Flow - RTL Design, HDL Coding, Synthesis, Verification, simulation, DFT, ATPG, STA, CTS, Timing, State Machine VLSI Concepts - Schematic, Layout, RC extraction, Floor Planning, APR, Analog Circuit, Sizing ... - 2015 Sep 20
... Parallel Processors, HPC, FLOPS ASIC Design Flow - RTL Design, HDL Coding, Synthesis, Verification, simulation, DFT, ATPG, STA, CTS, Timing, State Machine VLSI Concepts - Schematic, Layout, RC extraction, Floor Planning, APR, Analog Circuit, Sizing ... - 2015 Sep 20
Project Design
Oakton, VA
... EDA Tools Simulation : Cadence -NCSim, NC -Verilog, ModelSim, Synopsys-VCS, Aldec - Active HDL Lint Tools : Cadence -HAL Synthesis : XILINX ISE, ALTERA- QUARTUS, Synopsys- Design Compiler (DC) Hardware Modelling : MATLAB, SCILAB, SIMULINK STA : ... - 2015 Feb 27
... EDA Tools Simulation : Cadence -NCSim, NC -Verilog, ModelSim, Synopsys-VCS, Aldec - Active HDL Lint Tools : Cadence -HAL Synthesis : XILINX ISE, ALTERA- QUARTUS, Synopsys- Design Compiler (DC) Hardware Modelling : MATLAB, SCILAB, SIMULINK STA : ... - 2015 Feb 27
Manager Customer Service
Ashburn, VA
... • Plans, organizes, assigns, prioritizes, and delegates the work of dispatch sta ff. • Assists with screening of new a pplicants and makes recommendations for hiring, termination or disciplinary actions, Provides instruction to new hires (dispatch ... - 2015 Feb 16
... • Plans, organizes, assigns, prioritizes, and delegates the work of dispatch sta ff. • Assists with screening of new a pplicants and makes recommendations for hiring, termination or disciplinary actions, Provides instruction to new hires (dispatch ... - 2015 Feb 16
Engineer Design
Washington, DC
Peijian Yuan (US citizen) Phone: 202-***-**** E-mail: acgpa3@r.postjobfree.com OBJECTIVE Seeking engineering position on Hardware/Embedded system/FPGA design and firmware coding. SUMMARY * ***rs of experience in leading design of appliance product... - 2014 Nov 12
Peijian Yuan (US citizen) Phone: 202-***-**** E-mail: acgpa3@r.postjobfree.com OBJECTIVE Seeking engineering position on Hardware/Embedded system/FPGA design and firmware coding. SUMMARY * ***rs of experience in leading design of appliance product... - 2014 Nov 12
Medical Training
Washington Grove, MD
... Urine Microscopy System • Stago STA- R Mechanical Detection System • GEM 4000 Blood Gas System • Uricon- NE Refractometer • PFA- 100 Platelet Function System • HISTOCOMPATIBILITY AND MOLECULAR TECHNOLOGY SKILLS BD FACSCalibure • OpenGene HIV Seq. ... - 2014 Jul 21
... Urine Microscopy System • Stago STA- R Mechanical Detection System • GEM 4000 Blood Gas System • Uricon- NE Refractometer • PFA- 100 Platelet Function System • HISTOCOMPATIBILITY AND MOLECULAR TECHNOLOGY SKILLS BD FACSCalibure • OpenGene HIV Seq. ... - 2014 Jul 21