Soham Sinha

*****, ****** **** ******, *****-****7 682-***-**** acxwud@r.postjobfree.com

OBJECTIVE

Seeking a Full time employment position in the area of ASIC/SOC Design, Digital Logic,RTL Design and Validation/Verification, Static Timing Analysis, High Speed Digital Circuits design EDUCATION

University of Florida, Gainesville, FL, USA Aug 2014 –May 2016 Master of Science (MS) – Electrical & Computer Engineering Recipient of Academic Achievement Award

GPA: 3.39/4.0

Courses taken: VLSI Circuits & Technology; Bipolar Analog IC Design; Intro To Nano Devices; VLSI Device Design; RF Circuits and Systems; Advanced VLSI Design; Microwave IC Design; Advanced Antenna Systems Design; Future of Microelectronic circuits

WEST BENGAL INSTITUTE OF TECHNOLOGY, Kolkata (WBUT), India Aug 2007-May 2011 Bachelor of Technology (B.Tech) - Electronics and Communication Core Courses taken: VLSI Circuits Design; EDA for VLSI design; Digital Electronics; Analog Electronics; Analog Electronics; Computer Organization and Architecture; Microprocessor programming and Architecture; Circuits & Signals. WORK EXPERIENCE

TATA CONSULTANCY SERVICES (TCS), Kolkata, India Sept 2011-June 2014 Worked as SYSTEMS ENGINEER

Worked for a semiconductor designer client and worked on their memory controller ASIC Design project. Designed RTL Codes(Verilog),Ran Simulations to get precise output, Developed testbenches to verify the design. Worked on MODELSIM platform

Was also responsible for designing optimized layout for small sub blocks within the ASIC. Got valuable experience on VLSI design flow process, was responsible for RTL-GDSII delivery of designs for submodules within ASIC, optimized design at the transistor level and logic level to adhere to strict timing requirements.(Cadence SOC Encounter for placement and routing, Synopsys Design Compiler tools used for synthesis),Did STA using Synopsys Primetime to find out violating elements and optimized it’s transistor sizing to meet timing requirement. Worked on Unix platform and gained valuable experience on PERL, Shell Scripting

CENTER FOR ELECTRONICS TEST ENGINEERING June to August 2010

Worked as an intern.

Designed and implemented Digital Circuits at the RTL level, gate level and layout level in 90 nm node

Gained experience in Verilog,Cadence Spectre and Virtuoso, L-Edit, S-Edit PROJECTS

Design of a low power All Digital Phase Locked Loop

Designed a GRO based all digital phase locked loop. I designed the phase detector and the time to digital converter of the PLL The RTL design was done in Xilinx using Verilog, synthesized using Synopsys Design Compiler and the final layout was generated using Cadence SOC Encounter on TSMC 250nm technology. Design of a Round Robin Request Arbiter (RTL TO GDSII)

Designed a request arbiter system using round robin algorithm. It supported 4 independent blocks.

RTL implementation done in Xilinx ISE using Verilog, synthesized using Design Compiler, layout generated and optimized power and timing analyzed in SOC Encounter RTL TO GDSII Design of a 8 bit Sequence Detector.

Designed a programmable 8 bit sequence detector to detect a sequence as programmed by the user. RTL implementation done using Verilog in Xilinx ISE, Logic synthesis on Design Compiler and APR performed on SOC Encounter.

4X1 6T SRAM Cell Design in TSMC 250nm Technology

Designed a 4X1 6-transistor SRAM cell complete with sense amplifier, pre-charge and decode circuit. Schematic was done in Cadence Spectre and designed an optimized layout in Cadence virtuoso with proper DRC and LVS match. Determined important parameters like cell area, static noise margin, capacitance, read and write access times. Verification of a FIFO Memory system using SystemVerilog Verified a FIFO memory system by building an Object Oriented Verification environment using SystemVerilog including DUT, Scoreboard, Generator, Driver

Design of a 1 Gbps communication link between Earth and Moon

Designed a wireless link between earth and moon using Ku band and QPSK modulation scheme. The transceiver architecture was designed in Agilent ADS.BER of less than 10^-5 and a proper EVM(Error vector magnitude)was achieved. Link Budget analysis was done using Syscalc6.

Design of a 2.5 GHz CMOS Low Noise Amplifier

Designed a microwave transistor based low noise amplifier operating in the 2.44 GHz frequency using Agilent ADS.

Gain of 16.66 dB and a noise figure of around .983 dB was obtained.

Custom layout of the low noise amplifier(including bond pads) was designed in Cadence Virtuoso using TSMC 0.18 um technology

SKILLS

Tools : Cadence Spectre, Encounter, Virtuoso, Synopsys DC Compiler, Synopsys Primetime NCSim, LTSpice IV, Xilinx 14.1,Agilent ADS,Syscalc6,HFSS,ANISYS,MATLAB

Programming Language: C, JAVA, PLSQL

Scripting Language: PERL, Shell Scripting HDLs: Verilog, VHDL, SystemVerilog,ASIC DESIGN FLOW,SYNTHESIS, Concepts about Clock tree Synthesis,CDC,SYNCHRONIZERS,Timing Optimization, SOC Verification using SystemVerilog, Assertion based Verification, OVM,UVM

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