Education

The George Washington University (GWU) - Washington, DC December 2014

Master of Science, Electrical and Computer Engineering – 3.57/4.0 GPA

Gujarat Technological University (GTU) - Gujarat, India May 2012

Bachelor of Engineering, Electronics and Communication – 8.03/10.0 CGPA

Relevant Coursework - VLSI CMOS Design and Simulation, Design & Testing of VLSI Circuits, Microcomputer System Architecture, Modeling of VLSI Circuits/FPGA, VLSI Design, Grid and Cloud Computing, C programming, Digital Logic Design, Integrated Circuits and Application, Digital Communication, Microcontroller, Microprocessor Design, DSP, OOD (C SoC Verification on Udemy

Technical Skills

Programming Language - Verilog, C, C++, Java, Python, Perl, System Verilog, TCL, Makefiles, VHDL, SQL

Software & Tools - Cadence virtuoso/spectra, Synopsys VCS, UVM, OVM, Primetime, Logic Analyzer, Oscilloscope, Altera Quartus II, Xilinx ISE, EDA Playground, ICC, Modelsim, Matlab, CPF, AWS EC2, AWS S3

Computer Architecture - CPU, Cache, SRAM, DRAM, Pipeline, NAND, Flash, Embedded and Parallel Processors, HPC, FLOPS

ASIC Design Flow - RTL Design, HDL Coding, Synthesis, Verification, simulation, DFT, ATPG, STA, CTS, Timing, State Machine

VLSI Concepts - Schematic, Layout, RC extraction, Floor Planning, APR, Analog Circuit, Sizing, Logic Gates, SoC, FPGA

Object Oriented Concepts - Data Structure, Programming with sorting and searching, Algorithm, OOD, SDLC

Platforms - Windows Server, UNIX, Linux, MS Office Suite

Professional Experience

Scalable System Research Labs June 2015 - Present

ASIC Design Intern

Working on vlcRAM modules with testing, it integrates with HMC DRAM used for server and verification of HMC modules.

Contribution in the design, testing and documentation of the cache controller block of the HMC with firmware design.

Develop understanding of overall architecture of the project and coordinate with other teams to achieve the overall goal.

The George Washington University (Computing Facility) May 2013 - May 2015

Technical Analyst

Assist in the development, installation and maintenance of computer systems of University labs.

Installed software packages using script and manually, configured network, documentation, working with windows and UNIX, debug BIOS and Installed driver, maintenance on devices like server etc. which increased life of asset by 2 years.

Projects

Multicore CPU Design (GWU) Spring2014

Designed the multicore CPU design using RTL Verilog coding with low power techniques which had ALU, Controller, Register bank, System Bus and Memory modules. Verified & tested logic synthesis design with Verilog test bench.

Performed timing and power analysis, functional coverage, logic validation reports, failure analysis and debugging.

EDA Tools Used: Synopsys VCS, Design Vision Language Used: Verilog

FPGA Based Graphics Processing Unit (GPU) (GWU) Spring2014

Designed functionality of graphics processing unit (GPU) on the FPGA board that rendered triangle based model. Used graphics pipeline technology and floating point Unit, displayed bunny picture on the monitor using thousands of triangles.

EDA Tools used: Altera Quartus II, Simvision and Design Vision Language Used: Verilog and C

Reference: Demonstration of the Project

ASIC Design and Verification of Tiny MIPS Processor (GWU) Spring2013

Implemented the entire TinyMIPS Processor using RTL Verilog HDL, verified using Verilog Test bench and Synthesis Design.

Obtained gate level simulation and verified using DFT Scan Chain insertion and generated ATPG Patterns with Tetramax.

Performed RTL-to-GDS, STA and Place & Route of the design using cadence Encounter Digital Implementation System.

EDA Tools Used: Cadence Virtuoso, Synopsys VCS, Simvision, Design Vision and Tetramax Language Used: Verilog

FPGA Based Skin Color Detector (GWU) Fall2013

Developed skin color detector on the FPGA board using a camera that can be used in video surveillance or biometrics.

Captured image stored on SDRAM & algorithm differentiates color & displayed pixels of skin color detected on monitor.

EDA Tools Used: Altera Quartus II, Design Vision and Simvision Language Used: Verilog

Reference: Demonstration of the Project

Induction Stove (GTU) Fall2011 – Spring2012

Design and executed induction stove using the concepts of Electromagnetics; magnetic Coil was used to generate heat.

Implemented circuit on PCB board using resisters, capacitor and inductor with switching IC. Analyzed and measure the Resistance, Inductance and Capacitance of circuits. Tested by applying different voltage, statistically analyzed the data.

Microcontroller and temperature sensor were used to control temperature.

Contact this candidate