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PCB Desinger

Location:
Parsippany, New Jersey, 07054, United States
Posted:
July 28, 2011
Email:
zaa0rh@r.postjobfree.com
Contact Info:
******@*********.***


KEVIN K. VUTUAN
** ******* ****
Parsippany, NJ *7054
Phone :( 973)-***-**** Email:zaa0rh@r.postjobfree.com

CAREER SUMMARY

Experienced with the use of CADENCE Concept/Allegro and MENTOR Graphics Board Station RE and broad knowledge in all areas of PCB layout design including schematic capture, netlist generation, component placement, physical layout, manual and/or auto routings, assembly and fabrication drawings with over 20 years of PCB layout experience in high-speed digital, RF and analog PCBs. Proven track record of completing fast and accurate designs that have been successfully manufactured. Proven ability to multitask and maintain priorities, to work effectively with the customer, design engineers, PCB fabricator, and to work independently and within a team.
Expertise includes:
• Skilled in the design of high density multilayer PCB’s using HDI, fine pitch BGA, surface mount, through-hole or mixed technology.
• Controlled impedance, high-speed diff pairs routing and net length matching.
• Creation of new drawings from Engineer’s sketches and fabrication and assembly drawings for outside vendors.
• Revising and maintaining existing drawings, layouts, and schematics.
• Easily adaptable to changes in software and processes.

PROFESSIONAL EXPERIENCE

ALCATEL-LUCENT 04/2011-07/2011
PCB Layout – Contract Position
In charge of schematic capturing and layout using Mentor Graphics Board Station RE and Expedition.

GENERAL DYNAMICS AIS 12/2010-04/2011
PCB Layout – Contract Position
Working on Mentor Graphics Board Station. Responsible for PCB designs from conception to manufacturing including library part creation, schematic capture, and layout of 10 GHz high speed board and documenting the design.

IBM TJ WATSON RESEARCH CENTER 12/2009–04/2011
PCB Layout – Contract Position
Working on Cadence Allegro V16.2. In charge of PCB and back plane designs layout of very large, dense and very complex multilayer cards. Set up the electrical constraints. All hand routing for differential pair, high-speed signals and majority of non-critical signals.

GENERAL DYNAMICS AIS 06//2009-12/2009
PCB Layout - Contract Position
In charge of building a component library, schematic capturing and layout using Mentor Graphics Board Station.

ALCATEL-LUCENT 06/1988 – 06/2009
PCB Layout Designer
In charge of PCB design layout of complex multilayer, high-speed digital, RF and analog PCBs. Support the development cycle from circuit design through to prototype manufacturing, testing, laboratory support, and manufacturing release. Work with design engineers, component engineers, engineering QC personnel and technicians in the troubleshooting or process analysis.

• 2006 to 2009. Working on Cadence Concept /Allegro V16.1 to do schematics, layout and fully documenting the designs. Creating constraint design rule in Allegro and using Spectra router for auto routing of the PCBs of GPONs project.

• 1999 thru 2006. Working on Mentor Graphics Board Station to do schematics, layout and documentation. Using CES to create design rule checking and RE for auto routing of the PCBs of SCL2000, Anymedia and Stinger projects for Switching and Access Systems.

• 1992 thru 1999. Working extensively with Network Wireless Systems. Made contribution to RF and digital circuit pack layout design in support of the CDMA, TDMA and GSM projects.

• 1988 thru 1992. Design RF, Analog and Digital PCBs. In charge of schematic capturing, layout, editing, auditing and documenting the designs of Military projects.

AT&T BELL LABORATORIES SUMMER 1987
Summer Internship – Learned various aspect of:
• Schematic capture and PCB layout.
• Completing the audits, drill/test data, plots and artwork and creating files for Fabrication Manufacture.

EDUCATION

AAS, Electrical Engineering Technology – June 1988 from Bronx Community College, NY. GPA 3.8/4.0